What is Complex Programmable Logic Device(CPLD)

What is Complex Programmable Logic Device(CPLD)

Complex Programmable Logic Devices (CPLDs) are digital integrated circuits with programmable logic cells and interconnections used to implement a variety of digital logic functions for a wide range of applications, including system control, signal processing, and interface management.

The logic blocks in a CPLD (Complex Programmable Logic Device) are similar to those in a small-scale PLD (Programmable Logic Device). Typically, a logic block contains 4 to 20 macrocells. Each macrocell typically consists of a product term array, a product term allocator, and programmable registers. Each macro cell has multiple configurations and can be used in cascade, so complex combinational logic and timing logic functions can be realized. For more highly integrated CPLDs, embedded array blocks with on-chip RAM/ROM are also usually provided.

Programmable interconnect channels are mainly used to connect the interconnect network between logic blocks, macrocells and input/output pins. Input/output blocks (I/O blocks) provide the interface between the internal logic and the device I/O pins.

For CPLDs with larger logic sizes, JTAG (Joint Test Action Group) boundary-scan test circuits are also typically built in, allowing for comprehensive and thorough system testing of programmed high-density programmable logic devices. In addition, in-system programming is also possible through the JTAG interface.

Due to the integration process, integration scale and different manufacturers, a variety of CPLD partition structure, logic units and other aspects of the large differences. These differences make CPLDs widely applicable to meet the needs of different applications.

Fundamentals

The basic principle of CPLDs is to implement digital logic functions through programmable logic units and programmable interconnections. These logic units can be configured as a variety of logic gates and flip-flops, and the interconnect network allows these logic units to be interconnected to realize the desired circuit function.The configuration of a CPLD is typically generated by user-supplied high-level hardware description language (HDL) code or graphical design tools, and then loaded into the device to enable it to perform a specific logic function.

Technology

CMOS EPROM (Erasable Programmable Read-Only Memory): Early CPLD devices used CMOS EPROM technology. This technology allows logic functions to be programmed on the chip, but once programmed they cannot be erased or reprogrammed. These devices typically require a physical erase operation to clear the configuration.

EEPROM (Electrically Erasable Programmable Read-Only Memory): EEPROM technology provides erasable programming in CPLDs. Unlike CMOS EPROMs, EEPROMs allow multiple erasures and reprogramming, making CPLD configuration more flexible. This allows the designer to configure and test multiple times during the development process.

Flash Memory: Flash memory is a non-volatile memory technology that is also used for CPLD programming. It has a high density and is erasable and reprogrammable. Flash memory typically provides longer data retention times and higher reliability.

SRAM (Static Random-Access Memory): SRAM programming technology is used in some CPLD models.SRAM allows configuration data to be loaded and stored dynamically so the CPLD can remain configured after power is turned off. This type of programming is suitable for applications that require instantaneous configuration changes.

Composition of Complex Programmable Logic device(CPLD)

 Here are the main components of a CPLD:

 

Logic Cells or Macrocells: CPLDs consist of an array of logic cells or macrocells. Each logic cell is a configurable unit that can perform various logic functions, such as AND, OR, XOR, and NOT. It also typically includes a flip-flop for sequential logic operations. The logic cells are the primary building blocks for creating custom logic circuits.

Programmable Interconnects: CPLDs have a matrix of programmable interconnects that allow you to route signals between the logic cells and other components within the device. These interconnects are critical for creating the desired connections between logic cells to implement the desired logic functions.

Input/Output Blocks (IOBs): IOBs are responsible for interfacing the CPLD with external devices. They provide input and output pins that can be connected to external components or other parts of the digital system. IOBs often include features like voltage level translation, pull-up/pull-down resistors, and bidirectional capabilities.

Fixed Function Blocks (Optional): Some CPLDs include fixed function blocks that provide specialized functionality. These blocks may include clock management resources, memory elements (e.g., flip-flops), and counters. The availability of these blocks can vary depending on the specific CPLD model.

Configuration Memory: CPLDs require a configuration memory that stores the logic configuration for the device. This memory holds the information needed to define the behavior of the logic cells and interconnects. Common configuration memory types include Flash memory, SRAM (Static Random-Access Memory), or anti-fuse technology.

Clock Distribution Network: CPLDs often include a clock distribution network that allows for the distribution of clock signals to various parts of the device. This network ensures that all parts of the CPLD are synchronized to the same clock signal when necessary.

JTAG Interface: Many CPLDs feature a JTAG (Joint Test Action Group) interface, which allows for device programming, debugging, and testing. The JTAG interface is commonly used during the configuration process.

Power Supply Pins: Like any electronic component, CPLDs require power to operate. They have power supply pins for providing the necessary voltage levels to the device. These pins may include VCC (positive supply voltage) and GND (ground) connections.

Structure of Complex Programmable Logic Device(CPLD)

EPM7128S devices:

• Logic Array Blocks (LABs): each CPLD typically contains multiple logic array blocks that are used to implement combinational logic and timing logic functions. In the EPM7128S you mentioned, each logic array block (LAB) typically includes a set of macro cells that can be used to configure different logic functions.
• Macrocells: Each macrocell can be configured for either combinational logic or temporal logic operation. Macrocells typically include logic arrays, product term selection matrices, and programmable registers, which are used to implement specific logic functions.
• I/O Control Blocks: CPLDs typically have input/output control blocks for interfacing with external devices. These control blocks manage the input and output channels of the device to enable communication with the external world.
• Programmable Interconnect Array (PIA): A programmable interconnect array is used to connect different logic elements and macrocells in order to implement the desired logic function. It provides flexible signal routing.
• Global Bus: The Global Bus is used to connect different logic array blocks in order to realize larger logic functions.

XCR3064XL devices:

• Logic Blocks: The XCR3064XL device contains multiple logic blocks, each of which typically includes a set of macro cells. These logic blocks are used to implement different logic functions.
• Zero Power Interconnect Array: This is an interconnect network used to connect different function blocks and macrocells. It allows signals to be routed between different sections.
• I/O Unit: The I/O unit allows the device to communicate with the external world. It provides input and output pins to connect to external devices.
• Each CPLD model may have different features and resources, but they usually follow a similar structure that includes logic elements, programmable interconnects, input/output interfaces, and configuration memory. The designer uses these elements to configure the CPLD to implement the desired digital logic functions.

Product Models of Complex Programmable Logic Device(CPLD)

CPLD (Complex Programmable Logic Device) is a highly integrated digital circuit chip, which can realize complex logic functions, and at the same time has programmability and reconfigurability.CPLD is widely used in embedded systems, which can be used for control, communication, data processing and so on.

1. Altera MAX II series

Altera MAX II series is a low-power, high-performance CPLD products, using 5V or 3.3V power supply, with low power consumption, high speed, high reliability and other characteristics. This series of products includes MAX II EPM240, EPM570, EPM1270 and other models, of which EPM240 is the smallest model with 240 logic cells and 4Kb of memory, while EPM1270 is the largest model with 1270 logic cells and 64Kb of memory. These models can meet the needs of different application scenarios, such as control, communication, and data processing.

2. Xilinx CoolRunner-II series

Xilinx CoolRunner-II series is a low-power, high-performance CPLD product with 1.8V or 2.5V power supply. The series includes CoolRunner-II XC2C32, XC2C64, and XC2C128 models, of which XC2C32 is the smallest model with 32 logic cells and 1Kb of memory, while XC2C128 is the largest model with 128 logic cells and 4Kb of memory. These models can meet the needs of different application scenarios such as control, communication, data processing, etc.

3. Lattice MachXO2 Series

Lattice MachXO2 series is a kind of low-power and high-performance CPLD products with 1.2V or 3.3V power supply. The series includes MachXO2-256, MachXO2-640, and MachXO2-1200 models, of which MachXO2-256 is the smallest model with 256 logic cells and 2Kb of memory, while MachXO2-1200 is the largest model with 1200 logic cells and 64Kb of memory. These models can fulfill the needs of different application scenarios such as control, communication, data processing, etc.

4. Actel ProASIC3 Series

Actel ProASIC3 series is a kind of low-power and high-performance CPLD products with 1.2V or 3.3V power supply. The series includes ProASIC3 A3P015, A3P030, A3P060 models, of which A3P015 is the smallest model with 15K logic cells and 512Kb memory, while A3P060 is the largest model with 60K logic cells and 2Mb memory. These models can meet the needs of different application scenarios, such as control, communication, and data processing.

Applications of Complex Programmable Logic Device(CPLD)

CPLD Model	Features	Manufacturer	Applications	Advantages	Disadvantages
Altera EPM7128S	- 128 macrocells	Intel (formerly Altera)	- Glue logic - Bus interface - State machines	- Low power consumption - Fast response times	- Limited capacity for complex designs
Xilinx CoolRunner XCR3064XL	- 64 macrocells	Xilinx	- Bus interface - Display control	- Low power consumption - Fast response times	- Limited capacity for complex designs
Lattice Semiconductor MachXO2	- Up to 6864 Look-Up Tables (LUTs) - On-chip oscillators	Lattice Semiconductor	- Glue logic - Display control - Sensor interface	- Low power consumption - High I/O density	- Limited resources for very large designs
Atmel ATF150x	- Up to 128 macrocells - In-system programmability	Atmel (now part of Microchip Technology)	- Glue logic - Motor control - Embedded control	- In-system programmability - Wide range of temperature grades	- Smaller macrocell count compared to some competitors
Cypress (formerly Cypress) PAL CE22V10	- 10 macrocells - Low power	Cypress (formerly Cypress Semiconductor)	- Glue logic - Simple state machines	- Low power consumption - Cost-effective	- Limited macrocell count - Limited resources for complex designs

In short,

• Bonding logic in the system for connecting different components.
• Bus interface management, such as I2C, SPI and UART buses.
• Finite State Machine (FSM) implementations for controlling different states of a system.
• Timer and counter applications for generating precise time signals.
• Digital signal processing for filtering, data processing and waveform generation.
• Display control, e.g. LED matrix and LCD control.
• Automotive electronics, such as engine control units (ECUs) and instrument panel displays.
• Industrial automation, including PLCs (programmable logic controllers) and sensor interfaces.
• Communication devices, such as routers and switches.

Advantages and Disadvantages of Complex Programmable Logic Device(CPLD)

Advantages of CPLDs (Complex Programmable Logic Devices):

• Flexibility: CPLDs are highly versatile and can be programmed to perform a wide range of digital logic functions, making them suitable for a variety of applications.
• Rapid Prototyping: They are ideal for rapid prototyping and iterative design processes because of their reprogrammability.
• Fast Response Time: CPLDs offer fast response times, making them suitable for applications where low latency is crucial.
• Low Power Consumption: Compared to some other programmable logic devices like FPGAs, CPLDs tend to consume less power, making them suitable for battery-powered applications.
• Cost-Effective: CPLDs are often more cost-effective than designing custom ASICs for small to medium-scale digital designs.
• In-System Programming: Many CPLDs support in-system programming, allowing for easy updates and changes in the field without replacing the hardware.
• Integration of Logic and I/O: CPLDs typically integrate logic cells and I/O pins, simplifying the interface with other digital components.

Disadvantages of CPLDs:

• Limited Logic Capacity: CPLDs have a finite number of logic cells, which can be a limitation for complex designs. Larger designs may require FPGAs or ASICs.
• Complex Design Tools: Designing for CPLDs can sometimes require specialized software tools, which may have a learning curve for new users.
• Limited Resources: Some CPLDs may have limited on-chip resources for features like memory or specialized functions.
• Limited Performance: While CPLDs offer good performance for many applications, they may not match the speed and performance capabilities of high-end FPGAs.
• Non-Volatile Configuration: In some cases, CPLD configurations are volatile, meaning they must be loaded each time the device powers up. This can be a drawback in applications requiring instant-on functionality.
• Bounded I/O Pins: The number of I/O pins on a CPLD is limited, which can be a constraint in designs that require a large number of input and output connections.

Differences Between CPLD, PLD and FPGA

What is the difference between PLD, CPLD and FPGA?

Different manufacturers call it differently,

PLD (Programmable Logic Device) is a general term for programmable logic devices, early multi-EEPROM process, based on the product term (Product Term) structure. 

FPGA (Field Programmable Gate Array) refers to Field Programmable Gate Array, first invented by Xilinx. Most of them are SRAM process, based on Look Up Table (LOTR) structure, with external EPROM for configuration.

Xilinx calls PLDs with SRAM process and EPROM for external configuration FPGAs, and PLDs with Flash process (similar to EEPROM process) and multiplicative term structure CPLDs; Altera calls its PLDs FPGAs.

Altera's own PLD products: MAX series (EEPROM process), FLEX/ACEX/APEX series (SRAM process) are called CPLD, that is, the complex PLD (Complex PLD), the

As FLEX/ACEX/APEX series is also a SRAM process, to plug-in configuration with the EPROM, the use of the same as Xilinx's FPGA, so many people Altera's FELX/ACEX/APEX series of products is also called FPGA.

The main difference in structure,

1. Logic blocks of different granularity.

Logic block refers to the PLD chip according to the structure of the functional modules, it has a relatively independent combination of logical arrays, blocks rely on interconnect system connection. FPGA in the CLB is a logic block, which is characterized by a small granularity, the input variables for the 4 ~ 8, the output is 1 ~ 2, and thus just a logical unit, each chip has dozens to nearly a thousand such units. CPLD logic block granularity is larger, usually dozens of inputs and one or two dozen outputs, each chip is divided into a few pieces. Some lower integration (such as ATV2500) is simply not divided into blocks. Obviously, such a coarse block structure is not as flexible as FPGAs.

2. Different logic interconnection structure

CPLD logic block interconnect is a hub, which is characterized by equal delay, the delay between any two blocks is equal, this structure brings great convenience to the designer; FPGA interconnect is distributed, the delay with the system layout, [the application scope is also different]: [the application scope is also different]: [the application scope is also different].

The scope of application is also different,

Logic systems can usually be divided into two major types.

One is logic-intensive: such as cache control, DRAM control and DMA control, etc., they only need a small amount of data processing power, but the logic relationship is generally complex.

The other category is data-intensive: data-intensive requires a large amount of data processing capacity, its applications are mostly found in the field of communications.

Learn Digital Logic Circuits using CPLD(Video)